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M67201A/M67202A
512 9 & 1 K 9 CMOS Parallel FIFO
Introduction
The M67201A/202A implement a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The Expansion logic allows unlimited expansion in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information are required for the TEMIC FIFOs. Address pointers are automatically incremented with the write pin and read pin. The 9 bits wide data are used in data communications applications where a parity bit for error checking is necessary. The Retransmit pin reset the Read pointer to zero without affecting the write pointer. This is very useful for retransmitting data when an error is detected in the system. Using an array of eigh transistors (8 T) memory cell and fabricated with the state of the art 1.0 m lithography named SCMOS, the M 67201A/202A combine an extremely low standby supply current (typ = 1.0 A) with a fast access time at 25 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 5 W. For military/space applications that demand superior levels of performance and reliability the M 67201A/202A is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D D D D First-in first-out dual port memory 512 x 9 organisation (M 67201A) 1024 x 9 organisation (M 67202A) Fast access time 20*, 25, 35, 45, 55 ns, commercial, industrial and automotive 20*, 25, 30, 40, 50 ns, military D Wide temperature range : - 55C to + 125C D 67201AL/202AL low power 67201AV/202AV very low power D Fully expandable by word width or depth
* Preview. Please Consult Sales.
D D D D D D D D
Asynchronous read/write operations Empty, full and half flags in single device mode Retransmit capability Bi-directional applications Battery back-up operation : 2 V data retention TTL compatible Single 5 V 10 % Power Supply (1) High performance SCMOS technology
(1) 3.3 V versions are also available. Please consult sales.
MATRA MHS Rev. D (11 April. 97)
1
M67201A/M67202A
Interface
Block Diagram
Pin Configuration
SO plastic 28 pin 300 mils(*) DIL plastic 28 pin 300 mils DIL ceramic 28 pin 300 mils FP 28 pin 400 mils (Preview) SO/DIL (top view)
INDEX
32 pin LCC and PLCC
LCC (top view) W NC VCC I4 I3 I8 I5
(*) On request only.
2
GND NC R Q4 Q5
Q3 Q8
W I8 I3 I2 I1 I0 XI FF Q0 Q1 Q2 Q3 Q8 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC I4 I5 I6 I7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R
I2 I1 I0 XI FF Q0 Q1 NC Q2
432 32 31 30 1 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 14 15 16 17 18 19 20
I6 I7 NC FL/RT RS EF XO/HF Q7 Q6
MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
Pin Names
NAMES
I0-8 Q0-8 W R RS EF Inputs Outputs Write Enable Read Enable Reset Empty Flag
DESCRIPTION
NAMES
FF XO/HF XI FL/RT VCC GND
DESCRIPTION
Full Flag Expansion Out/Half-Full Flag Expansion IN First Load/Retransmit Power Supply Ground
Signal Description
Data In (I0 - I8)
Data inputs for 9 - bit data pointers to the first location. A reset is required after power-up before a write operation can be enabled. Both the Read Enable (R) and Write Enable (W) inputs must be in the high state during the period shown in figure 1 (i.e. tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. The Half-Full flag (HF will be reset to high after Reset (RS).
RESET (RS)
Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both internal read and write Figure 1. Reset.
Notes :
1. EF, FF and HF may change status during reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS.
Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be maintained in the rise time of the leading edge of the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any current read operation. Once half of the memory is filled, and during the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and remain in this state until the difference between the write and read pointers is less than MATRA MHS Rev. D (11 April. 97)
or equal to half of the total available memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF, allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is blocked from W, so that external changes to W will have no effect on the full FIFO stack. 3
M67201A/M67202A
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not with standing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 - Q8) will return to a high impedance state until the next Read operation. When all the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the "final" read cycle, but inhibiting further read operations whilst the data outputs remain in a high impedance state. Once a valid write operation has been completed, the Empty Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO stack is empty, the internal read pointer is blocked from R, so that external changes to R will have no effect on the empty FIFO stack.
Full Flag (FF)
The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 512/1024 writes.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer is equal to the write pointer, indicating that the device is empty.
Expansion Out/Half-full Flag (XO/HF)
This is a dual-purpose output. In the single device mode, when Expansion In (XI) is connected to ground, this output acts as an indication of a half-full memory. After half the memory is filled and on the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and will remain set until the difference between the write and read pointers is less than or equal to half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last memory location.
First Load/Retransmit (FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to ground to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by connecting the Expansion In (XI) to ground. The M 67201A/202A can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed low. A retransmit operation will set the internal read point to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the high state during retransmit. The retransmit feature is intended for use when a number of writes equals to or less than the depth of the FIFO have occured since the last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), in accordance with the relative locations of the read and write pointers.
Data Output (Q0 - Q8)
DATA output for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state.
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain modes.
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MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
Functional Description
Operating Modes Single Device Mode
A single M 67201A/202A may be used when the application requirements are for 512/1024 words or less. Figure 2. Block Diagram of Single 512 x 9 and 1024 x 9.
HF (HALF-FULL FLAG) WRITE (W) 9 DATAIN (I) (R) 9 READ
The M 67201A/202A is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 2). In this mode the Half-Full Flag (HF), which is an active low output, is shared with Expansion Out (XO).
M
67201A 67202A
Q
DATAOUT
FULL FLAG (FF) RESET (RS)
(EF) EMPTY FLAG (RT) RETRANSMIT
EXPANSION IN (XI)
WIDTH EXPANSION MODE
Word width may be increased simply by connecting the corresponding input control signals of multiple devices.
Status flags (EF, FF and HF) can be detected from any device. Figure 3 demonstrates an 18-bit word width by using two M 67201A/202A. Any word width can be attained by adding additional M 67201A/202A.
Figure 3. Block Diagram of 512 / 1024 x 18 FIFO Memory Used in Width Expansion Mode.
HF 9 DATAIN (1) (R) READ WRITE FULL FLAG RESET (RS) 9 9 XI XI 18 (Q)DATAOUT Note : 3. Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width expansion configuration. Do not connect any output control signals together. (W) (FF) HF 9
18
M
67201A/202A
M
67201A/202A
(EF) EMPTY FLAG (RT) RETRANSMIT
MATRA MHS Rev. D (11 April. 97)
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M67201A/M67202A
Table 1 : Reset and retransmit Single Device Configuration/Width Expansion Mode
INPUTS MODE
Reset Retransmit Read/Write
INTERNAL STATUS XI
0 0 0
OUTPUTS EF
0 X X
RS
0 1 1
RT
X 0 1
Read Pointer
Location Zero Location Zero Increment(4)
Write Pointer
Location Zero Unchanged Increment(4)
FF
1 X X
HF
1 X X
Note : 4. Pointer will increment if flag is high.
Table 2 : Reset and First Load Truth Table Depth Expansion/Compound Expansion Mode
INPUTS MODE
Reset First Device Reset All Other Devices Read/Write
INTERNAL STATUS XI
(5) (5) (5)
OUTPUTS EF
0 0 X
RS
0 0 1
FL
0 1 X
Read Pointer
Location Zero Location Zero X
Write Pointer
Location Zero Location Zero X
FF
1 1 X
Note : 5. XI is connected to XO of previous device. See fig. 5.
Depth Expansion (Daisy Chain) Mode
The M 67201A/202A can be easily adapted for applications which require more than 512/1024 words. Figure 4 demonstrates Depth Expansion using three M 67201A/202A. Any depth can be achieved by adding additional 67201A/202A. The M 67201A/202A operate in the Depth Expansion configuration if the following conditions are met : 1. The first device must be designated by connecting the First Load (FL) control input to ground. 2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin of each device must be connected to the Expansion In (XI) pin of the next device. See figure 4. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires that all EF's and all FFs be ORed (i.e. all must be set to generate the correct composite FF or EF). See figure 4. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode.
Compound Expansion Module
It is quite simple to apply the two expansion techniques described above together to create large FIFO arrays (see figure 5).
Bidirectional Mode
Applications which require data buffering between two systems (each system being capable of Read and Write operations) can be created by coupling M 67201A/202A as shown in figure 6. Care must be taken to ensure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device on which W is in use ; EF is monitored on the device on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.
Data Flow - Through Modes
Two types of flow-through modes are permitted : a read flow-through and a write flow-through mode. In the read flow-through mode (figure 17) the FIFO stack allows a
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MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
single word to be read after one word has been written to an empty FIFO stack. The data is enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the first write edge and remains on the bus until the R line is raised from low to high, after which the bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating temporary reset and then will be set. In the interval in which R is low, more words may be written to the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; however, the same word (written on the first write edge) presented to the output bus as the read pointer will not be incremented if R is low. On toggling R, the remaining words written to the FIFO will appear on the output bus in accordance with the read cycle timings. In the write flow-through mode (figure 18), the FIFO stack allows a single word of data to be written immediately after a single word of data has been read from a full FIFO stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading edge of W. The W line must be toggled when FF is not set in order to write new data into the FIFO stack and to increment the write pointer.
Figure 4. Block Diagram of 1536 x 9 / 3072 x 9 FIFO Memory (Depth expansion).
XO W 6 9 FF 9 M 67201A 67202A EF 9 Q FL VCC R
FULL
FF 9
M 67201A 67202A
EF
EMPTY
FL
FF 9 RS
M 67201A 67202A
EF
FL XI
Figure 5. Compound FIFO Expansion.
Q0 - Q8 Q0 - Q8 R . W . RS M 67201A/202A DEPTH EXPANSION BLOCK Q9 - Q17 Q9 - Q17 M 67201A/202A DEPTH EXPANSION BLOCK Q(N-8) - QN Q(N-8) - QN M 67201A/202A DEPTH EXPANSION BLOCK
I0 - I8 I0 - I8 I9 - I17
I9 - I17 I(N-8) - IN
I(N-8) - IN
Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4. 7. For Flag detection see section on Width Expansion and Figure 3.
MATRA MHS Rev. D (11 April. 97)
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M67201A/M67202A
Figure 6. Bidirectional FIFO Mode.
WA FFA IA 0-8
M
M 67201A M 67202A QB 0-8
RB EFB HFB
SYSTEM A
SYSTEM B
QA 0-8 RA HFA EFA
M
M 67201A M 67202A
IB 0-8 WB FFB
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC - GND) . . . . . . . . . . . . . . . . . . - 0.3 V to 7.0 V Input or Output voltage applied : . . . . (GND - 0.3 V) to (Vcc + 0.3 V) Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . -65 C to + 150 C
OPERATING RANGE
Military Industrial Commercial Automotive
OPERATING SUPPLY VOLTAGE
Vcc = 5 V 10 % Vcc = 5 V 10 % Vcc = 5 V 10 % Vcc = 5 V 10 %
OPERATING TEMPERATURE
- 55 C to + 125 C - 40 C to + 85 C 0 C to + 70 C - 40 C to + 125 C
DC Parameters
M 67201A M 67202A - 20 (Preview) COM
ICCOP (8) Operating p g supply current l Standby y supply current l Power down current V L V L V L 140 140 1.5 1.5 40 400
M 67201A M 67202A - 25
M 67201A M 67202A - 30 MIL
140 140 1.5 1.5 80 800
M 67201A M 67202A - 35 COM
120 120 1.5 1.5 40 400
IND IND MIL COM MIL AUTO AUTO
150 150 1.5 1.5 80 800 125 125 1.5 1.5 40 400 140 140 1.5 1.5 80 800
IND UNIT AUTO
140 140 1.5 1.5 80 800 mA mA mA mA A A
VALUE
Max Max Max Max Max Max
ICCSB (9)
ICCPD (10)
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MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
DC Parameters (continued)
M 67201A M 67202A - 40 Parameter
ICCOP (8)
M 67201A M 67202A - 45 COM
80 80 1.5 1.5 40 400
M 67201A M 67202A - 50 MIL
100 100 1.5 1.5 80 800
M 67201A M 67202A - 55 COM
70 70 1.5 1.5 40 400
Description
Operating p g supply current l Standby y supply current l Power down current
Version
V L V L V L
MIL
120 120 1.5 1.5 80 800
IND AUTO
120 120 1.5 1.5 80 800
IND UNIT AUTO
100 100 1.5 1.5 80 800 mA mA mA mA A A
VALVAL UE
Max Max Max Max Max Max
ICCSB (9)
ICCPD (10)
Notes :
8. Icc measurements are made with outputs open. F = F max 9. R = W = RS = FL/RT = VIH. 10. All input = Vcc.
M 67201A/M67202A PARAMETER
ILI (11) ILO (12) VIL (13) VIH (13) VOL (14) VOH (14) C IN (15) C OUT (15) Notes : 11. 12. 13. 14. 15.
DESCRIPTION
Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage Output high voltage Input capacitance Output capacitance
- 20/- 25/- 30/
1 10 0.8 2.2 0.4 2.4 8 8
- 35/- 40/- 45/- 50/- 55
1 10 0.8 2.2 0.4 2.4 8 8
UNIT
A A V V V V pF pF
VALUE
Max Max Max Min Max Min Max Max
0.4 Vin Vcc. R = VIH, 0.4 VOUT VCC. VIH max = Vcc + 0.3 V. VIL min = -0.3 V or -1 V pulse width 50 ns. Vcc min, IOL = 8 mA, IOH = -2 mA. This parameter is sampled and not tested 100 % - TA = 25 C - F = 1 MHz.
AC Test Conditions
Input pulse levels Input rise/Fall times : 5 ns Input timing reference levels Output reference levels Output load : Gnd to 3.0 V : 1.5 V : 1.5 V : See figure 7
Figure 7. Output Load.
5V TO OUTPUT PIN 333 500
30 pF*
* includes jig and scope capacitance
MATRA MHS Rev. D (11 April. 97)
9
M67201A/M67202A
M 67201A/202A M 67201A/202A M 67201A/202A M 67201A/202A
SYMBOL (16)
SYMBOL (17)
PARAMETER (18) (22)
COM, IND, COM, IND, MIL, AUTO MIL, AUTO - 20 - 25
PREVIEW
MIL ONLY - 30
COM, IND, AUTO - 35
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ TWLWL TWLWH TWHWL TDVWH TWHDX TRSLWL TRSLRSH TWHRSH TRSHWL TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset to EF low Reset to HF/FF high Read low to EF low Read high to FF high Read width after EF high Write high to EF high Write low to FF low Write low to HF low Read high to HF high Write width after FF high tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRSR tRTC tRT tRTS tRTR Read cycle time Access time Read recovery time Read pulse width (19) Read low to data low Z (20) Write low to data low Z (20, 21) Data valid from read high Read high to data high Z (20) Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time 30 - 10 20 5 5 5 - 30 20 10 12 0 30 20 20 10 30 20 20 10 - - - - 20 - - - - 20 - 20 - - - - - 15 - - - - - - - - - - - - - 30 30 20 20 - 20 20 30 30 - 35 - 10 25 5 5 5 - 35 25 10 15 0 35 25 25 10 35 25 25 10 - - - - 25 - - - - 25 - 25 - - - - - 18 - - - - - - - - - - - - - 35 35 25 25 - 25 25 35 35 - 40 - 10 30 5 10 5 - 40 30 10 18 0 40 30 30 10 40 30 30 10 - - - - 30 - - - - 30 - 30 - - - - - 20 - - - - - - - - - - - - - 40 40 30 30 - 30 30 40 40 - 45 - 10 35 5 10 5 - 45 35 10 18 0 45 35 35 10 45 35 35 10 - - - - 35 - - - - 35 - 35 - - - - - 20 - - - - - - - - - - - - - 45 45 30 30 - 30 30 45 45 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE
PREVIEW
RESET CYCLE
PREVIEW
RETRANSMIT CYCLE
PREVIEW
PREVIEW
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MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
M 67201A/202A M 67201A/202A M 67201A/202A M 67201A/202A
SYMBOL (16)
SYMBOL (17)
MIL ONLY PARAMETER (18) (22) - 40
COM, IND, MIL, AUTO - 45
MIL ONLY - 50
COM, IND, AUTO - 55
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ TWLWL TWLWH TWHWL TDVWH TWHDX TRSLWL TRSLRSH TWHRSH TRSHWL TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset to EF low Reset to HF/FF high Read low to EF low Read high to FF high Read width after EF high Write high to EF high Write low to FF low Write low to HF low Read high to HF high Write width after FF high - - - - 40 - - - - 40 50 50 30 35 - 35 35 50 50 - - - - - 45 - - - - 45 55 55 40 40 - 40 40 55 55 - - - - - 50 - - - - 50 60 60 45 45 - 45 45 60 60 - - - - - 55 - - - - 55 65 65 50 50 - 50 50 65 65 - ns ns ns ns ns ns ns ns ns ns tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ tWC tWPW tWR tDS tDH tRSC tRS tRSS tRSR tRTC tRT tRTS tRTR Read cycle time Access time Read recovery time Read pulse width (19) Read low to data low Z (20) Write low to data low Z (20, 21) Data valid from read high Read high to data high Z (20) Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time 50 - 10 40 5 10 5 - 50 40 10 20 0 50 40 40 10 50 40 40 10 - 40 - - - - - 25 - - - - - - - - - - - - - 55 - 10 45 5 10 5 - 55 45 10 20 0 55 45 45 10 55 45 45 10 - 45 - - - - - 25 - - - - - - - - - - - - - 65 - 15 50 10 15 5 - 65 50 15 30 0 65 50 50 15 65 50 50 15 - 50 - - - - - 30 - - - - - - - - - - - - - 70 - 15 55 10 15 5 - 70 55 15 30 0 70 55 55 15 70 55 55 15 - 55 - - - - - 30 - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE
RESET CYCLE
RETRANSMIT CYCLE
MATRA MHS Rev. D (11 April. 97)
11
M67201A/M67202A
M 67201A/202A M 67201A/202A M 67201A/202A M 67201A/202A
SYMBOL (16)
SYMBOL (17)
PARAMETER (18) (22)
COM, IND, COM, IND, MIL, AUTO MIL, AUTO - 20 - 25
PREVIEW
MIL ONLY - 30
COM, IND, AUTO - 35
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL tXOL tXOH tXI tXIR tXIS Read/Write to XO low Read/Write to XO high XI pulse width XI recovery time XI set-up time - - 20 10 10 20 20 - - - - - 25 10 10 25 25 - - - - - 30 10 10 30 30 - - - - - 35 10 10 35 35 - - - ns ns ns ns ns
M 67201A/202A
M 67201A/202A
M 67201A/202A
M 67201A/202A
SYMBOL (16)
SYMBOL (17)
MIL ONLY PARAMETER (18) (22) - 40
COM, IND, MIL, AUTO - 45
MIL ONLY - 50
COM, IND, AUTO - 55
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL Notes : 16. 17. 18. 19. 20. 21. 22. tXOL tXOH tXI tXIR tXIS Read/Write to XO low Read/Write to XO high XI pulse width XI recovery time XI set-up time - - 40 10 10 40 40 - - - - - 45 10 10 45 45 - - - - - 50 10 15 50 50 - - - - - 55 10 15 55 55 - - - ns ns ns ns ns
STD symbol. ALT symbol. Timings referenced as in ac test conditions. Pulse widths less than minimam value are not allowed. Values guaranteed by design, not currently tested. Only applies to read data flow-through mode. All parameters tested only.
Figure 8. Asynchronous Write and Read Operation.
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MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
Figure 9. Full Flag from Last Write to First Read.
Figure 10. Empty Flag from Last Read to First Write.
Figure 11. Retransmit.
Note :
23. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
MATRA MHS Rev. D (11 April. 97)
13
M67201A/M67202A
Figure 12. Empty Flag Timing
Figure 13. Full Flag Timing
Figure 14. Half-Full Flag Timing.
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MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
Figure 15. Expansion Out.
Figure 16. Expansion In.
Figure 17. Read Data Flow - Through Mode.
MATRA MHS Rev. D (11 April. 97)
15
M67201A/M67202A
Figure 18. Write Data Flow - Through Mode.
Ordering Information
TEMPERATURE RANGE C M PACKAGE 3P DEVICE 67201AL SPEED 25 FLOW
M = 5 V version L = 3.3 V version 1P = 28 pin DIL ceramic 300 mils 3P = 28 pin DIL plastic 300 mils *TI = 28 pin SOL plastic 300 mils *UI = 28 pin SOJ plastic 300 mils 4J = 32 pin LCC rectangular S1 = 32 pin PLCC DP = 28 pin FP 400 mils (Preview) CP = Side brazed 28 pins 300 mils 0 = Dice form C = Commercial I = Industrial A = Automotive M = Military S = Space * On request only 0 -40 -40 -55 -55 to +70C to +85C to +125C to +125C to +125C 67201 = 512 x 9 FIFO 67202 = 1024 x 9 FIFO AL = Low power AV = Very low power
20 ns 25 ns 30 ns 35 ns 40 ns 45 ns 50 ns 55 ns
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX :R : RD :D
= = = = = = = = = = = =
MHS standards MIL STD 883 Class B or S MIL STD 883 + PIND test SCC 9000 level B/C Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape and reel Tape and reel dry pack Dry pack
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MATRA MHS Rev. D (11 April. 97)
M67201A/M67202A
Military and Space Versions
The following tables give package/consumption/access time/process flow available combinations
Temp. range Packages Consumption
V L 25
Access Time (ns)
30 40 50
Std process 67201A
Mil flows (including SMD5962-87531 SMD5962-89863) D D D X D D D X D
RT process 67201F
Mil flows Space flows
M
1P 4J CP DP 0 4J CP DP 0
1 1 1 1 X 1 1 1 X
D D D D D
X X X X X X X X X
D D D X X D D X X
D D D X X D D X X
D D D X D D D X D
S
D
D D X D
Temp. range
Packages
Consumption
V L 25
Access Time (ns)
30 40 50
Std process 67202A
Mil flows (including SMD5962-89536) D D D X D D D X D
RT process 67202F
Mil flows Space flows (including SCC9301032)
M
1P 4J CP DP 0 4J CP DP 0
D D D D X D D D X
D D D D D
X X X X X X X X X
D D D X X D D X X
D D D X X D D X X
D D D X D D D X D
S
D
D D X D
D = product in production X = call sales office for availibility
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
MATRA MHS Rev. D (11 April. 97)
17

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